The present invention relates generally to stacking chips and to an improved thermal extraction from the stacked chips structure and, more particularly, to interconnecting chips that electrically form a system-on-a-package (SOP) or which are attached to another SOP, while physically being folded into a three-dimensional arrangement which significantly reduces the footprint of the final assembly.
As systems become more complex, the need for integrated circuits with multiple functions increases, making it necessary to fabricate chips of different functions separately and assemble them into a system or a sub-system. By way of example, one may need to assemble the logic of a processor module, a memory chip and a wireless transceiver as a final product. Processing these chips does not allow building them concurrently on a single chip. It is therefore necessary to package each chip individually, and subsequently assemble the chips on a printed circuit board (PCB) that contains the electrical connections. The present example results in having three individual chips consuming valuable space on the PCB. It should also be noted that each chip generates waste heat, which must be extracted to keep the product running efficiently and reliably.
It is known in the art that the yield is generally much higher in packages consisting of smaller dies. It would therefore be highly advantageous to use multiple smaller dies, such that smaller high yield chips are interconnected to combine their respective functions in a single package.
Interconnections between packages are advantageously provided by flexible wires, as will be described hereinafter in the present invention, wherein the flexibility and strength of various metal/polymer combinations has already been demonstrated for a variety of applications such as, in the article “Adhesion Strength and Peeling Angle Measured on the Polyimide/Cr Interfaces” by Jin-Won Choi et al., published in the Proceedings of the 2000 Materials Research Society Symposium, Vol. 629, pp. FF5.10.1-FF10.1.10 by the Materials Research Society. The article describes the use of polyimide/Cr/Cu structures fabricated on BPDA-PDA polyimide, and the correlation between adhesion strength and peeling angle. It has been determined that without depending on the plastic bending of metal film or polyimide substrate, the adhesion strength increases with the peeling angle during T-peel tests.
In a paper on materials properties entitled “Maximizing Flex Life in Flexible Printed Circuits” published by the Rogers Corp. of Chandler, Ariz., web URL http://www.rogerscorporation.com, are described ways of maximizing the flex life of printed circuits by taking full advantage of the material's flexibility to conform to the packaging during fabrication.
In another publication “Adhesiveless Copper on Polyimide Substrate with Nickel-Chromium Tiecoat” by Tad Bergstresser et al. presented at the IPC Expo 2003 (web URL http://www.circuiTree.com/CDA/ArticleInformation/features/BNP_Features_Item/0,2133,100993,00.html) are discussed the characteristics of copper on polyimide substrates with nickel-chromium tiecoat. The peel strength after thermal aging, pressure cooker exposure, and exposure to gold plating are measured and compared to results for other tiecoat constructions. The NiCr tiecoat acts as a barrier between copper and polyimide and reduces adhesion loss after thermal aging as compared to no tiecoat. The NiCr tiecoat significantly improves adhesion retention after plating from neutral potassium gold cyanide bath. Its performance is comparable to samples with chromium tiecoat and better than samples with monel tiecoat. Peel loss after gold plating results from copper undercut, at the copper-polyimide interface, by components of the plating solution.
Typical stacked die applications require that the chips be thinned to a range of 50 to 125 μm. This results in special handling requirements as well as special tooling to deal with warpage. The typical stacked die arrangements also require high placement accuracy, as one chip is placed upon another which, otherwise, ends up with electrical failures. Other problems associated with stacked die applications include excessive epoxy covering bonding pads and special substrate design rules and loop heights for wire bonding have to be applied to prevent shorts. The present invention solves these and other problems while still providing many of the same benefits such as reduced space, weight savings and even enhanced performance.